A basic phase locked loop (PLL) has a phase detector which provides a phase detect output signal indicative of the phase difference between a loop clock signal and a reference clock signal. The phase detector provides the phase detect output signal to an input of a loop filter. The loop filter is a low-pass filter which provides an output voltage level indicative of the length of time the phase detector detects the two clock signals are out of phase. The output of the loop filter drives an input of a voltage controlled oscillator (VCO). The VCO then provides a clock output signal having a desired frequency. The clock output signal is divided in a loop divider to provide the loop clock signal. Thus, the PLL is able to generate the clock output signal having a frequency that is many times greater than that of the reference clock signal, based on the value of the loop divider.
A digital PLL uses an oscillator which responds to a digital code provided by a digital loop filter. This oscillator is variously referred to in the art as a VCO, a digital VCO (DVCO), a digitally-controlled oscillator (DXCO), or the like, although the term VCO will be used herein. One type of VCO used in digital PLLs is known as a pulled-crystal VCO. The pulled-crystal VCO is useful in applications in which the nominal clock output frequency is fixed but the actual frequency may vary by a relatively small amount. One case in which a pulled-crystal VCO is useful is a telecommunications system in which the far end provides data at a nominal rate which may vary by a certain amount, but does not provide a separate clock signal.
The pulled-crystal VCO uses not only a conventional resistor and inverter to bias a crystal, but also a variable capacitance. The pulled-crystal VCO changes the amount of load capacitance on the crystal's terminals to "pull" the frequency by relatively-small amounts. A capacitor digital-to-analog converter (CDAC) network provides the variable capacitance based on the loop filter's digital code. However, known CDACs present some problems, including testability, clock output signal jitter, and circuit design.
For proper testability, it is desirable to determine whether the CDAC's capacitors have been fabricated properly. Fabrication problems may result in either open circuits into one of the capacitor's terminals, or short circuits between the capacitor's terminals. In the CDAC section of the pulled-crystal VCO, short circuits may be easily tested. A test code connects all capacitors to the crystal terminals, and a testing apparatus detects a short if the amount of leakage current is excessive. Open circuit testing, however, is normally considered impractical. With a functional test it is possible to detect open capacitors, but this test requires a very long time for the clock output signal to stabilize to detect the small changes in output frequency. For example, CDAC capacitors may affect the clock output signal frequency by as little as fifteen parts-per-million (ppm). Thus the functional test must be run for enough cycles to detect a deviation from a frequency change of 15 ppm. Furthermore, each capacitor must be individually tested, multiplying this test period by the number of capacitors in the CDAC.
Another problem is clock output signal jitter. Switching additional capacitors onto crystal terminals results in a "glitch", which can introduce jitter into the clock output signal. One known method to minimize the effects of switching capacitors into the array was taught by Imamaru in U.S. Pat. No. 5,117,206, issued on May 26, 1992. Imamaru slowly changes the impedance of switching elements in order to avoid the effects of discretely switching a new capacitor into the circuit. However, Imamaru's capacitor array requires additional circuitry to generate the voltages provided to the switching elements.
The requirements for high performance and low power consumption also make circuit design of the crystal's inverter difficult. The inverter must be strong enough to drive a widely-varying capacitive load without switching transients, which cause signal jitter. The inverter must have matched pullup and pulldown characteristics in order to maintain proper duty cycle. However, the stronger the inverter, the higher the power consumption. Also, the pulled-crystal oscillator outputs a sinusoidal waveform which must be converted into a digital clock, further complicating circuit design.
Each of these problems exists to varying degrees in known pulled-crystal VCOs. It would thus be desirable to have an oscillator which simultaneously alleviates all these problems.